Summer Bootcamp - Increase class-based (OOP) support and develop UVM elements for PCIe AXI Bridge verification environment - #237205

Job Description and Requirements

Executive summary:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. It is state-of-the art in random constraint verification environments. PCIe AXI Bridge is a sub-module of the PCIe (PCI Express) IIP family of cores (EP/RC/DM) and is regressed in a Stand-Alone-Testbench (SATB).
SATB verification environment has at its heart a System Verilog VMM component that uses the Synopsys AMBA VIP (Verification IP) for handling AXI protocol as well as a newly developed PCIe VIP component. It is also a class based testbench that aims to have as much as code reusability, scalability, and industry best code practices as possible.
As UVM became the industry standard for ASIC (Application Specific Integrated Circuit) verification, efforts have been made to port parts of the verification environment to UVM and use UVM based Verification IPs. Currently we have a hybrid verification environment.
Porting the existing VMM/System Verilog testbench environment to UVM creating UVM elements is a key task that will enable this methodology migration.
The proposal for this summer job is to develop UVM elements and integrate them in our VMM environment while also increasing our class bass testbench support.
Main skills to develop:
Technical skills:
• Evaluates and exercises various aspects of the development flow. May include such items as Verilog/System Verilog development, scripting, functional simulation, constraint development and verification coverage metrics (functional coverage and code coverage).
• Participate in evaluation and troubleshooting of systems and workflows.
• Good problem-solving skills.
• Programming skills in one or more languages such as System Verilog and verification methodologies (VMM and UVM).
• Work on state-of-the-art products and use innovative technologies.
Non-technical skills:
• Exposure to team collaboration software that helps teams organize, discuss, and complete shared work.
• Improve/practice communication skills in English.
• Explore investigation, analysis, and problem-solving skills.
• Sharpen the desire to learn and explore innovative technologies
• Contact with stable and supportive work environment where integrity, execution excellence, passion and integrity are valued.

Goals:
This summer job exposes interns to the vast Synopsys EDA (Electronic Design Automation) portfolio, Verification IPs, daily work/collaboration tools and methodologies interacting with the existing SATB verification flow and state of art tools. In the end we will expect the following results:
• Familiarity with System Verilog and UVM Methodology.
• Rework and fine tune blocks of code into structures, methods, and properties to have a more class based testbench.
• Implement/create UVM base elements.
• Test developed code in our regression flow.

Project planning/tasks:
Two phases should be considered.
Learning phase:
• System Verilog, VMM and UVM training.
• Get used to SATB structure and PCIe verification environment, create a client and run the first regressions.
Development phase:
•Create packages for global code, rework pieces of code into OOP base structures, methods, and properties.
• Create UVM elements based on our VMM/System Verilog existing ones.
• Integrate and try to run a full regression with the new updates.